PRESERVE8
THUMB
INCLUDE MyAsmVar.S
INCLUDE VarOfs.S
INCLUDE M0_Regs.S
Buffer1 EQU 0x20000000
Buffer2 EQU 0x20000210
SampleRate EQU 48000000 / 22050
AREA RESET, CODE, READONLY
Reset_ PROC
DCD 0x20001000 ; Top of Stack
DCD Reset ; Reset Handler
DCD Handler ; NMI Handler
DCD Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD Handler ; PendSV Handler
DCD Handler ; SysTick Handler
; External Interrupts
DCD Handler ; Window Watchdog
DCD 0 ; Reserved
DCD Handler ; RTC through EXTI Line
DCD Handler ; FLASH
DCD Handler ; RCC
DCD Handler ; EXTI Line 0 and 1
DCD Handler ; EXTI Line 2 and 3
DCD Handler ; EXTI Line 4 to 15
DCD 0 ; Reserved
DCD Handler ; DMA1 Channel 1
DCD Handler ; DMA1 Channel 2 and Channel 3
DCD Handler ; DMA1 Channel 4 and Channel 5
DCD Handler ; ADC1
DCD Handler ; TIM1 Break, Update, Trigger and Commutation
DCD Handler ; TIM1 Capture Compare
DCD 0 ; Reserved
DCD Handler ; TIM3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD Tim14_Int ; TIM14
DCD Handler ; TIM15
DCD Handler ; TIM16
DCD Handler ; TIM17
DCD Handler ; I2C1
DCD Handler ; I2C2
DCD Handler ; SPI1
DCD Handler ; SPI2
DCD Handler ; USART1
DCD Handler ; USART2
ALIGN
RamBase RN R7
ENTRY
Reset LDR R0,=0x20000000 ; RAMI SILELIM
LDR R1,=0x20001000
MOVS R2,#0
RamSil STR R2,[R0]
ADDS R0,#4
CMP R0,R1
BLT RamSil
LDR R0,=SYSCFG_BASE
LDR R1,=0x00000000
STR R1,[R0,#SYSCFG_CFGR1] ; Main Flash memory seçildi
LDR R0,=FLASH_BASE
MOVS R1,#0x11 ; 1 Wait State, Prefetch Enb
STR R1,[R0,#FLASH_ACR]
; SYSCFG clock enable
LDR R0,=RCC_BASE
LDR R1,=0x00001001 ; SysClk Enable
STR R1, [R0,#RCC_APB2ENR]
LDR R1,=0x00280000 ; PLL x 12, PLL Source HSI
STR R1, [R0,#RCC_CFGR]
; LDR R1,=0x01000000 ; PLL On
LDR R1,=0x010000AB ; PLL On
STR R1, [R0,#RCC_CR]
WaitPLL LDR R1, [R0,#RCC_CR]
LDR R2,=0x02000000
TST R1,R2
BEQ WaitPLL
LDR R1,=0x00280002 ; PLL x 12, PLL Source HSI, PLL Select
STR R1, [R0,#RCC_CFGR]
LDR R1,=0x00060000
STR R1,[R0,#RCC_AHBENR] ; GPIOA, GPIOB Clk Enb
LDR R1,=0x00005001 ; USART1, SPI1 Clk Enb
STR R1,[R0,#RCC_APB2ENR]
LDR R1,=0x00000100 ; TIMER14 Clk Enb
STR R1,[R0,#RCC_APB1ENR]
; GPIOA TANIMLARI
INP EQU 0x0 ; Input Mode
OUT EQU 0x1 ; Output Mode
ALT EQU 0x2 ; Alternate Mode
ANA EQU 0x3 ; Analog Mode
LDR R0,=GPIOA_BASE
LDR R1,=(INP<<30 :OR: \
ALT<<28 :OR: \
ALT<<26 :OR: \
INP<<24 :OR: \
INP<<22 :OR: \
INP<<20 :OR: \
INP<<18 :OR: \
INP<<16 :OR: \
ALT<<14 :OR: \
ALT<<12 :OR: \
ALT<<10 :OR: \
ALT<<8 :OR: \
ALT<<6 :OR: \
ALT<<4 :OR: \
INP<<2 :OR: \
INP)
STR R1,[R0,#GPIOA_MODER]
PP EQU 0x0 ; Push Pull Mode
OD EQU 0x1 ; Open Drain Mode
LDR R1,=(PP<<30 :OR: \
PP<<28 :OR: \
PP<<26 :OR: \
PP<<24 :OR: \
PP<<22 :OR: \
PP<<20 :OR: \
PP<<18 :OR: \
PP<<16 :OR: \
PP<<14 :OR: \
PP<<12 :OR: \
PP<<10 :OR: \
PP<<8 :OR: \
PP<<6 :OR: \
PP<<4 :OR: \
PP<<2 :OR: \
PP)
STR R1,[R0,#GPIOA_OTYPER]
MS EQU 0x1 ; Medium speed
LS EQU 0x2 ; Low speed
HS EQU 0x3 ; H1gh Speed
LDR R1,=(LS<<30 :OR: \
LS<<28 :OR: \
LS<<26 :OR: \
LS<<24 :OR: \
LS<<22 :OR: \
LS<<20 :OR: \
LS<<18 :OR: \
LS<<16 :OR: \
LS<<14 :OR: \
LS<<12 :OR: \
LS<<10 :OR: \
LS<<8 :OR: \
LS<<6 :OR: \
LS<<4 :OR: \
LS<<2 :OR: \
LS)
STR R1,[R0,#GPIOA_OSPEEDR]
FL EQU 0x0 ; No pull-up, pull-down
PU EQU 0x1 ; Pull-up
PD EQU 0x2 ; Pull-down
LDR R1,=(FL<<30 :OR: \
PD<<28 :OR: \
PU<<26 :OR: \
FL<<24 :OR: \
FL<<22 :OR: \
FL<<20 :OR: \
FL<<18 :OR: \
FL<<16 :OR: \
FL<<14 :OR: \
FL<<12 :OR: \
FL<<10 :OR: \
PU<<8 :OR: \
PU<<6 :OR: \
FL<<4 :OR: \
FL<<2 :OR: \
FL)
STR R1,[R0,#GPIOA_PUPDR]
; GPIOB TANIMLARI
LDR R0,=GPIOB_BASE
LDR R1,=(INP<<30 :OR: \
INP<<28 :OR: \
INP<<26 :OR: \
INP<<24 :OR: \
INP<<22 :OR: \
INP<<20 :OR: \
INP<<18 :OR: \
INP<<16 :OR: \
INP<<14 :OR: \
INP<<12 :OR: \
INP<<10 :OR: \
INP<<8 :OR: \
INP<<6 :OR: \
INP<<4 :OR: \
OUT<<2 :OR: \
INP)
STR R1,[R0,#GPIOB_MODER]
LDR R1,=(LS<<30 :OR: \
LS<<28 :OR: \
LS<<26 :OR: \
LS<<24 :OR: \
LS<<22 :OR: \
LS<<20 :OR: \
LS<<18 :OR: \
LS<<16 :OR: \
LS<<14 :OR: \
LS<<12 :OR: \
LS<<10 :OR: \
LS<<8 :OR: \
LS<<6 :OR: \
LS<<4 :OR: \
LS<<2 :OR: \
LS)
STR R1,[R0,#GPIOB_OSPEEDR]
;*********************************************************************
; USART Init
;*********************************************************************
LDR R0,=GPIOA_AFRL ; USART1'I PA3 VE PA4'E ATAYALIM
LDR R1,=0x41100 ; PA2 VE PA2 AF1 (USART), PA4 TIMER14 HARD 34.SAYFA
STR R1,[R0]
LDR R0,=USART1_BASE
MOVS R1,#0
STR R1,[R0,#USART1_CR1]
STR R1,[R0,#USART1_CR2]
LDR R1,=48000000 / 250000 ; 115200 baud
STR R1,[R0,#USART1_BRR]
MOVS R1,#0X0D
STR R1,[R0,#USART1_CR1]
;*********************************************************************
; T1mer14 Init
;*********************************************************************
LDR R0,=TMR14_BASE
LDR R1,=SampleRate
STRH R1,[R0,#TIM14_ARR]
MOVS R1,#0x6C
STRH R1,[R0,#TIM14_CCMR1]
MOVS R1,#0x03
STRH R1,[R0,#TIM14_CCER]
MOVS R1,#0x81
STRH R1,[R0,#TIM14_CR1]
LDR R1,=SampleRate / 2
STRH R1,[R0,#TIM14_CCR1]
MOVS R1,#1
STRH R1,[R0,#TIM14_DIER] ; Int Enb
B SD_INIT
ALIGN
LTORG
;*********************************************************************
; SDHardInit
; R0 = 0 Ok
; 1 Kart takili degil
; 2 Uyumsuz kart takilmis
;*********************************************************************
SD_INIT LDR RamBase,=_Sektor
BL SDHardInit
STRB R0,[RamBase,#CardStatus]
MOVS R0,#0
STR R0,[RamBase,#Sektor]
;*********************************************************************
; NESTED INTERRUPT CONTROLLER
;*********************************************************************
LDR R1,=NVIC_BASE+NVIC_ICDR0
LDR R0,=0XFFFFFFFF
STR R0,[R1,#0]; NVIC_ICDR0
STR R0,[R1,#4]; NVIC_ICDR1
; Tum intlarin onceligini sona alalim
LDR R2,=NVIC_BASE+NVIC_PRI0
STR R0,[R2,#0x00]; NVIC_PRI0
STR R0,[R2,#0x04]; NVIC_PRI1
STR R0,[R2,#0x08]; NVIC_PRI2
STR R0,[R2,#0x0C]; NVIC_PRI3
STR R0,[R2,#0x10]; NVIC_PRI4
STR R0,[R2,#0x14]; NVIC_PRI5
STR R0,[R2,#0x18]; NVIC_PRI6
STR R0,[R2,#0x1C]; NVIC_PRI7
MOVS R0,#0x13
MOVS R1,#0x7
BL Set_Priority ; Timer 14
B MyProg
;*********************************************************************
; R0 Int No
; R1 Int Priority (0...7)
; Dikkat R2,R3,R4,R5,R6 icerigi bozulur
;*********************************************************************
Set_Priority LDR R2,=NVIC_BASE+NVIC_PRI0
MOVS R4,R0
MOVS R3,#3
BICS R4,R3 ; Tek bir PRIO Registeri 4 Interruptin onceligini saklayabilir
ADDS R2,R4 ; Hangi PRIO registerine yukleyecegiz belli oldu
ANDS R3,R0 ; Int No kacinci 4 lude belli oldu
LSLS R3,#3 ; Register icindeki bit pozisyonu 8*N + 4
ADDS R3,#4 ; Int No Bit numarasi belli oldu
MOVS R5,#0x0F
LSLS R5,R3 ; Maske belli oldu
LDR R4,[R2] ; PRIOx Registerini okuduk
BICS R4,R5 ; PRIOx Registerinde ilgili bitler silindi
LSLS R1,R3 ; Int priorityi registerdeki ilgili bitlere gore siraladik
ORRS R1,R4 ; Ilgili bit alanina yerlestirdik
STR R1,[R2] ; Ilgili PRIOx registerine yazdik
LDR R2,=NVIC_BASE
CMPS R0,#32 ; Enable biti ISER0 dami ISER1 demi ?
BGE Ust_grup
LDR R3,[R2,#NVIC_ISER0]
MOVS R4,#1
LSLS R4,R0
ORRS R3,R4
STR R3,[R2,#NVIC_ISER0]
BX LR
Ust_grup LDR R3,[R2,#NVIC_ISER1]
MOVS R4,#1
SUBS R0,#32
LSLS R4,R0
ORRS R3,R4
STR R3,[R2,#NVIC_ISER1]
BX LR
Handler B .
INCLUDE SD_CARD.S
ALIGN
INCLUDE MyProg.S
ENDP
ALIGN
END